126 lines
4.0 KiB
Diff
126 lines
4.0 KiB
Diff
From 8a47615dd04a02fdae9691f5ad73fd5a5530c156 Mon Sep 17 00:00:00 2001
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From: hjl <hjl@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Tue, 16 Jan 2018 11:19:51 +0000
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Subject: [PATCH 8/9] x86: Add 'V' register operand modifier
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Add 'V', a special modifier which prints the name of the full integer
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register without '%'. For
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extern void (*func_p) (void);
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void
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foo (void)
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{
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asm ("call __x86_indirect_thunk_%V0" : : "a" (func_p));
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}
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it generates:
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foo:
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movq func_p(%rip), %rax
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call __x86_indirect_thunk_rax
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ret
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gcc/
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Backport from mainline
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2018-01-14 H.J. Lu <hongjiu.lu@intel.com>
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* config/i386/i386.c (print_reg): Print the name of the full
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integer register without '%'.
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(ix86_print_operand): Handle 'V'.
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* doc/extend.texi: Document 'V' modifier.
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gcc/testsuite/
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Backport from mainline
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2018-01-14 H.J. Lu <hongjiu.lu@intel.com>
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* gcc.target/i386/indirect-thunk-register-4.c: New test.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-7-branch@256736 138bc75d-0d04-0410-961f-82ee72b054a4
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---
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gcc/ChangeLog | 10 ++++++++++
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gcc/config/i386/i386.c | 13 ++++++++++++-
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gcc/doc/extend.texi | 3 +++
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gcc/testsuite/ChangeLog | 7 +++++++
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gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c | 13 +++++++++++++
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5 files changed, 45 insertions(+), 1 deletion(-)
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create mode 100644 gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
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diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
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index 8fb8902..1bbdd0c 100644
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--- a/src/gcc/config/i386/i386.c
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+++ b/src/gcc/config/i386/i386.c
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@@ -17941,6 +17941,7 @@ put_condition_code (enum rtx_code code, machine_mode mode, bool reverse,
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If CODE is 'h', pretend the reg is the 'high' byte register.
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If CODE is 'y', print "st(0)" instead of "st", if the reg is stack op.
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If CODE is 'd', duplicate the operand for AVX instruction.
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+ If CODE is 'V', print naked full integer register name without %.
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*/
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void
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@@ -17951,7 +17952,7 @@ print_reg (rtx x, int code, FILE *file)
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unsigned int regno;
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bool duplicated = code == 'd' && TARGET_AVX;
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- if (ASSEMBLER_DIALECT == ASM_ATT)
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+ if (ASSEMBLER_DIALECT == ASM_ATT && code != 'V')
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putc ('%', file);
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if (x == pc_rtx)
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@@ -17999,6 +18000,14 @@ print_reg (rtx x, int code, FILE *file)
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else
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code = GET_MODE_SIZE (GET_MODE (x));
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+ if (code == 'V')
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+ {
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+ if (GENERAL_REGNO_P (regno))
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+ code = GET_MODE_SIZE (word_mode);
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+ else
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+ error ("'V' modifier on non-integer register");
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+ }
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+
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/* Irritatingly, AMD extended registers use different naming convention
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from the normal registers: "r%d[bwd]" */
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if (REX_INT_REGNO_P (regno))
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@@ -18118,6 +18127,7 @@ print_reg (rtx x, int code, FILE *file)
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& -- print some in-use local-dynamic symbol name.
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H -- print a memory address offset by 8; used for sse high-parts
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Y -- print condition for XOP pcom* instruction.
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+ V -- print naked full integer register name without %.
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+ -- print a branch hint as 'cs' or 'ds' prefix
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; -- print a semicolon (after prefixes due to bug in older gas).
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~ -- print "i" if TARGET_AVX2, "f" otherwise.
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@@ -18342,6 +18352,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
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case 'X':
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case 'P':
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case 'p':
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+ case 'V':
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break;
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case 's':
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diff --git a/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c b/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
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new file mode 100644
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index 0000000..f0cd9b7
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--- /dev/null
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+++ b/src/gcc/testsuite/gcc.target/i386/indirect-thunk-register-4.c
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@@ -0,0 +1,13 @@
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+/* { dg-do compile } */
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+/* { dg-options "-O2 -mindirect-branch=keep -fno-pic" } */
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+
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+extern void (*func_p) (void);
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+
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+void
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+foo (void)
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+{
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+ asm("call __x86_indirect_thunk_%V0" : : "a" (func_p));
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+}
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+
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+/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_eax" { target ia32 } } } */
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+/* { dg-final { scan-assembler "call\[ \t\]*__x86_indirect_thunk_rax" { target { ! ia32 } } } } */
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--
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2.7.4
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